Redefining the boundary between software and silicon

fido is an acronym for flexible input, deterministic output. This captures two of the essential benefits of the architecture. “flexible input” refers to our UIC peripheral engine and “deterministic output” refers to the unique real-time and safety-critical features provided by the new architecture.

RTOS Kernel in a Chip

Innovasic took a fresh approach to the design of the fido family. We moved some very specific Real-Time Operating System (RTOS) functions into the silicon to provide exceptional real-time control capability and to allow our customers to develop and debug their code much faster than is possible on conventional microcontrollers. Context switching, context management, scheduling, priority control and memory protection are all built-in to the fido chip. We call this capability “RTOS Kernel in a Chip” and it doesn’t exist on other microcontrollers. For some applications, this capability eliminates the need for an RTOS altogether. For others, only a very small footprint RTOS may be needed.

Programmable I/O

We took the exact opposite approach with our peripheral set. We made the I/O peripherals programmable so that almost any permutation of I/O protocols can be supported by a single fido part number. Customers told us that they are often forced to use multiple members of a microcontroller family to address different I/O requirements. This not only causes inventory management issues, since multiple part numbers have to be purchased and managed in relatively low quantities, but it also raises the obsolescence concern again. Exposure to multiple part numbers increases the likelihood of encountering an end of life notice with at least one of these parts. By allowing the user to select the peripheral functionality in software, one fido part number can address multiple product designs.

KEY FEATURES OF THE FIDO1100

• Real-time 32-bit microcontroller
• New CISC architecture optimized for real-time
• CPU32+ (68000) instruction set compatible
• Context Manager (RTOS Kernel in a Chip)
  • On-chip priority based preemptive scheduler
  • 5 independent hardware contexts
  • Single clock cycle context switching
  • On-chip time- and space-partitioning
• Deterministic Cache
• Dedicated Peripheral Management Unit
• Universal I/O Controller (UIC) supporting:
  • 10/100 Ethernet
  • CAN
  • UART
  • SPI
  • SMBus
  • GPIO
  • MAC filtering
• Full featured two channel DMA with deterministic arbitration
• Zero-overhead Endian conversion
• Five counters and timers
• Two 32-bit timer control unit
• Watchdog timer
• Context timer
• External Bus Interface
• 8-bit or 16-bit interface
• Programmable chip selects
• SDRAM controller
• 24 KBytes high-speed SRAM
• Flat contiguous memory
• Non-aligned memory access
• Automatic sleep mode when contexts are inactive
• JTAG emulation and Debug Interface
• On-chip SPIDER debug tools
  • Unlimited trace buffer anywhere in memory
  • True on-chip single stepping (no emulation)
  • Single step one context while other run at speed
  • Context-aware breakpoints with minimal instrumentation
  • Break/watch points can be chained together to capture elusive bugs
• Library and support tools
• Eclipse IDE
• Customized GNU tool set
• Full library support
• UIC libraries
• Embedded communication stacks
• GPIO sample programs TCP/IP
• Standard 208 PQFP, TQFP and FBGA packaging
• 3.3V with 5V tolerant I/Os
• Industrial temperature grade
  

Applications

• Industrial Automation
• Motion Control
• Programmable Logic Controllers
• Communication Controllers
• Real-time Embedded Devices
• Instrumentation
• Safety-critical devices
• I/O modules